VHDL Implementation of Efficient Multimode Block Interleaver for WiMAX

Wireless communication is one of the most vibrant research areas in the communication field today. WLAN and WiMAX are emerging standards for wireless broadband communication system. OFDM is multiplexing technique used in above standards as it reduces inter symbol interference and multipath fading over wireless channel. Standards mentioned above can be implemented efficiently in FPGA. Interleaver plays a vital role in improving the performance of FEC codes in terms of Bit Error Rate over wireless channel. The complete Interleaver has been divided into two sub modules; address generator and interleaved memory. The proposed work presents that a modification in the FSM of address generator for WiMAX Interleaver provides a considerable improvement in terms of logic cells and slice flip flops used. Moreover using this modified address generator an efficient multimode WiMAX Interleaver has been implemented using VHDL. The simulation results and circuit parameters are also presented.